Memory cell arrays are generally configured to store data bits in individually addressable memory cells. The memory cells arc arranged in a series of rows and columns, and read/write voltages are applied to individual memory cells using row and column electrodes that are typically referred to as word lines and bit lines, respectively. Memory cell arrays usually have a word line associated with each row of memory cells and pairs of bitlines associated with each memory port. For a single-port memory, a single pair of bitlines is associated with each column, while in multi-port memories additional pairs of bitlines are provided. For example, dual-port memories have two pairs of bitlines associated with each column.
In order to obtain high memory density, memory cells are defined using small circuit areas. As a result, read/write signals propagating on one bitline can be coupled to one or more adjacent bitlines. Such coupling can be associated with inaccurate read/write operations, or can cause data loss in a memory cell. While adjacent bitlines can be shielded using parallel electrodes that are connected to a supply voltage or ground, such electrodes are undesirable in many applications because they use an appreciable amount of available circuit area. Accordingly, improved memories are needed.